KVIPS — Verification IP Suite

Verification IP that ships silicon

Enterprise-grade SystemVerilog UVM VIPs with production-ready regressions, built-in checkers, and Verilator-compatible flows.

3 Core VIPs
4 EDA Tools
100% UVM Compliant
Get Started VIP Catalog View on GitHub

Validated on Leading EDA Tools

Siemens Questa 2025.3_2 Synopsys VCS 2025.06_1 Cadence Xcelium 25.03.007 Verilator 5.x

Why Choose KVIPS?

⚡

Production Ready

Extensively tested and validated against industry-leading EDA simulators. Each VIP includes comprehensive regression suites.

🎯

UVM Compliant

Built on Accellera UVM 1.1d/1.2 standards with IEEE 1800 SystemVerilog. Seamlessly integrates with your existing testbenches.

🔧

Highly Configurable

Extensive configuration knobs for delay modeling, error injection, outstanding transactions, and protocol-specific features.

📊

Built-in Checkers

SystemVerilog Assertions (SVA) for protocol compliance, plus optional scoreboards for data integrity verification.

📚

Comprehensive Docs

Detailed user guides, API references, integration guides, and working examples for rapid deployment.

🔓

Vendor Neutral

No vendor lock-in. Pure SystemVerilog implementation works across Questa, VCS, Xcelium, and Verilator without modification.

Available Verification IPs

🔌

AXI4 Full

Stable v1.0

AMBA AXI4 Full Protocol VIP

  • Master & Slave agents with configurable memory model
  • INCR/FIXED/WRAP bursts (up to 256 beats)
  • Exclusive access support with reservation tracking
  • Multiple outstanding transactions (pipelined mode)
  • Configurable delays, backpressure, error injection
  • Comprehensive SVA protocol checkers
  • Built-in scoreboard for data verification
Documentation Quick Start
📡

APB (APB3/APB4)

Stable v1.0

AMBA APB3/APB4 Protocol VIP

  • Master & Slave agents for register access
  • Single-image APB3/APB4 with runtime switch
  • Configurable wait states (PREADY control)
  • PPROT & PSTRB support (APB4)
  • Error injection (PSLVERR)
  • Byte-lane selective writes (APB4)
  • Protocol assertions & scoreboard
Documentation Quick Start
🔗

AHB (AHB-Lite/Full)

Stable v1.0

AMBA AHB-Lite/Full Protocol VIP

  • Master & Slave agents with burst support
  • Runtime AHB-Lite/Full mode selection
  • INCR/WRAP bursts with stall handling
  • Variable HSIZE (byte to dword)
  • Error injection (OKAY/ERROR responses)
  • Configurable wait states
  • Comprehensive assertions & coverage
Documentation Quick Start
🚧

More VIPs Coming Soon

In Development

Roadmap:

  • AXI-Lite (Q2 2026)
  • AXI-Stream (Q3 2026)
  • PCIe Gen3/4/5 (Q4 2026)
  • USB 2.0/3.0 (2027)
  • I2C, SPI, UART (Q3-Q4 2026)

Contributions welcome! Check our contribution guidelines.

Technical Highlights

🎮 Flexible Sequencing

Rich library of pre-built sequences including:

  • Basic directed sequences
  • Constrained random sequences
  • Stress & corner-case sequences
  • Protocol-specific sequences

🔍 Debug & Observability

Comprehensive debug capabilities:

  • Transaction-level tracing
  • UVM transaction recording
  • Performance statistics
  • Runtime assertion control

⚙️ Coverage Driven

Built-in functional coverage:

  • Protocol feature coverage
  • Cross-coverage matrices
  • Transition coverage
  • Corner case tracking

Quick Start Example

Get up and running in minutes with KVIPS

# Clone the repository
git clone https://github.com/kiranreddi/kvips.git
cd kvips

# Run AXI4 example on Questa
cd axi4/examples/uvm_back2back/sim
./run_questa.sh +UVM_TESTNAME=axi4_b2b_test

# Run full regression
module load lsf
cd ../../..
make -C kvips/axi4/examples regress-questa USE_LSF=1
# Clone the repository
git clone https://github.com/kiranreddi/kvips.git
cd kvips

# Run AXI4 example on VCS
cd axi4/examples/uvm_back2back/sim
./run_vcs.sh +UVM_TESTNAME=axi4_b2b_test
# Clone the repository
git clone https://github.com/kiranreddi/kvips.git
cd kvips

# Run AXI4 example on Xcelium
cd axi4/examples/uvm_back2back/sim
./run_xcelium.sh +UVM_TESTNAME=axi4_b2b_test

Simple Integration

// Instantiate AXI4 interface
axi4_if #(
    .ADDR_W(32),
    .DATA_W(64),
    .ID_W(4)
) axi_if (
    .aclk(clk),
    .areset_n(rst_n)
);

// Configure and create agents
axi4_env_cfg cfg = new("cfg");
axi4_agent_cfg mst_cfg = new("mst_cfg");
mst_cfg.is_master = 1;
mst_cfg.vif = axi_if;
cfg.agent_cfgs.push_back(mst_cfg);

// Create environment
axi4_env env = axi4_env::type_id::create("env", this);
uvm_config_db#(axi4_env_cfg)::set(this, "env", "cfg", cfg);

// Start sequences
axi4_basic_write_seq seq = new("seq");
seq.start(env.get_master_sequencer(0));

By the Numbers

3
Protocol VIPs
4
EDA Tools
100%
UVM Compliant
∞
No Vendor Lock-in

Launch your verification stack in minutes

Curated quick starts, clean APIs, and battle-hardened regressions — ready for production.

Get Started Now Explore Documentation