AHB (AHB-Lite/AHB Full) Protocol Verification IP

📋 Overview

The KVIPS AHB VIP provides a comprehensive verification environment for AMBA AHB-Lite and AHB Full protocols in a single compiled image with runtime mode selection. It includes:

🔌 Protocol Mode Selection

The AHB VIP supports both AHB-Lite and AHB Full in a single compiled image. Select the mode at runtime:

# AHB-Lite mode (default) - single master, OKAY/ERROR responses only
+AHB_MODE=AHB_LITE

# AHB Full mode - extended features (arbiter support planned)
+AHB_MODE=AHB_FULL

🧪 RTL-DUT verification

The examples/uvm_dut/ environment drives a synthesizable, reset-initialized AHB RAM responder with the KVIPS master. Its six-test gate covers single transfers, INCR and WRAP bursts, fixed wait states, back-to-back stress, and AHB Full mode. Each simulator regression requires real read/write handshakes, zero responder errors, zero scoreboard mismatches, and wait-state evidence for the wait-state test.

make -C ahb/examples regress-rtl-questa USE_LSF=1
make -C ahb/examples regress-rtl-vcs USE_LSF=1
make -C ahb/examples regress-rtl-xcelium USE_LSF=1
make -C ahb/examples rtl-questa RTL_TEST=ahb_dut_full_mode_test PLUSARGS='+AHB_MODE=AHB_FULL'

Verilator runs the same DUT list in CI for portable coverage; commercial simulator logs are the evidence-bearing validation. See the AHB DUT verification guide.

🚀 Quick Start

Run Example Tests

Navigate to the AHB examples directory and run tests:

cd ahb/examples/

# List available tests
make list-tests

# Run smoke test on Questa
make questa TEST=ahb_smoke_test

# Run with AHB Full mode
make questa TEST=ahb_smoke_test PLUSARGS='+AHB_MODE=AHB_FULL'

# Run wait state test on VCS
make vcs TEST=ahb_wait_state_test

# Run stress test on Xcelium
make xcelium TEST=ahb_random_stress_test

# Run on Verilator
make verilator TEST=ahb_smoke_test

# Full Verilator regression
make regress-verilator

# RTL-DUT regression (commercial simulator)
make regress-rtl-questa USE_LSF=1

# Run with LSF (if tools require job scheduler)
make questa USE_LSF=1 TEST=ahb_smoke_test

📝 Note: SVA assertions are skipped under Verilator.

Available Test Cases

RTL-DUT tests

📐 Architecture

Component Hierarchy

ahb_env
├── ahb_agent (master)
│   ├── ahb_sequencer
│   ├── ahb_master_driver
│   └── ahb_monitor
├── ahb_agent (slave)
│   ├── ahb_sequencer
│   ├── ahb_slave_driver
│   └── ahb_monitor
├── ahb_scoreboard
└── ahb_txn_logger (optional)

Directory Structure

kvips/ahb/
├── sv/
│   ├── if/
│   │   └── ahb_if.sv              # AHB interface + clocking blocks
│   ├── assertions/
│   │   └── ahb_if_sva.svh         # Protocol assertions (SVA)
│   ├── pkg/
│   │   ├── ahb_types_pkg.sv       # Type definitions, enums
│   │   └── ahb_uvm_pkg.sv         # UVM package
│   └── uvm/
│       ├── ahb_cfg.svh             # Configuration object
│       ├── ahb_transaction.svh     # Transaction item
│       ├── ahb_sequencer.svh       # Sequencer
│       ├── ahb_master_driver.svh   # Master driver
│       ├── ahb_slave_driver.svh    # Slave driver
│       ├── ahb_monitor.svh         # Passive monitor
│       ├── ahb_scoreboard.svh      # Data integrity checker
│       ├── ahb_agent.svh           # Agent wrapper
│       ├── ahb_env.svh             # Environment
│       ├── ahb_sequences.svh       # Sequence library
│       └── ahb_txn_logger.svh      # Transaction logger
├── docs/
│   ├── user_guide.md              # Detailed usage guide
│   ├── integration_guide.md       # Integration instructions
│   ├── dut_verification.md        # RTL-DUT topology and evidence gate
│   ├── supported_features.md      # Feature list & roadmap
│   ├── assertions.md              # Assertion documentation
│   ├── testplan.md                # Test coverage plan
│   └── directory_structure.md     # File organization
├── examples/
│   ├── uvm_back2back/             # Self-contained VIP-to-VIP demo
│   └── uvm_dut/                   # KVIPS master to synthesizable RAM DUT
└── README.md                       # Quick reference

⚙️ Configuration

Key Configuration Knobs

class ahb_cfg extends uvm_object;
  
  // Protocol Mode
  ahb_mode_t mode = AHB_MODE_LITE;  // AHB_MODE_LITE or AHB_MODE_FULL
  
  // Slave Configuration - Wait States
  bit        allow_wait_states = 1;
  int unsigned min_wait = 0;        // Minimum wait cycles
  int unsigned max_wait = 5;        // Maximum wait cycles
  
  // Slave Configuration - Error Injection
  bit        err_enable = 0;        // Enable error injection
  bit [31:0] err_addr_lo = 0;       // Error range start
  bit [31:0] err_addr_hi = 0;       // Error range end
  int unsigned err_pct = 10;        // Error probability %
  
  // Master Configuration - Burst Policy
  bit        allow_bursts = 1;      // Enable burst transfers
  bit        allow_wrap = 1;        // Enable WRAP bursts
  int unsigned max_incr_len = 16;   // Max INCR burst length
  
  // Debug & Coverage
  bit        trace_enable = 0;      // Transaction tracing
  bit        coverage_enable = 1;   // Coverage sampling
  
  // Assertion Control
  bit        assertions_enable = 1; // Enable SVA checks
  
  // Address Configuration
  bit [31:0] addr_min = 32'h0000_0000;
  bit [31:0] addr_max = 32'hFFFF_FFFF;
  
endclass

Runtime Configuration via Plusargs

# Protocol mode selection
+AHB_MODE=AHB_LITE       # Default: AHB-Lite mode
+AHB_MODE=AHB_FULL       # AHB Full mode

# Debug options
+VIP_TRACE               # Enable transaction tracing
+UVM_VERBOSITY=UVM_HIGH  # Verbose UVM messaging

# Scoreboard options
+KVIPS_AHB_SB_WARN_UNINIT  # Warn on reads from uninitialized memory

📊 Supported Features

✅ Currently Supported (v0.1)

Protocol Support

• ✅ Single-bus, single-master operation (AHB-Lite style)
• ✅ Runtime mode selection: AHB-Lite vs AHB Full
• ✅ Basic responses: OKAY and ERROR
• ✅ Address/control pipelining with HREADY stall handling

Transfer Types

• ✅ SINGLE transfers
• ✅ INCR4/8/16 burst transfers
• ✅ WRAP4/8/16 burst transfers with wrap addressing
• ✅ Variable HSIZE (byte/half-word/word/double-word)

VIP Components

• ✅ Master agent: drives transfers with correct address/control vs data phasing
• ✅ Slave agent: responds with HREADYOUT/HRESP/HRDATA, captures writes
• ✅ Passive monitor: reconstructs completed transfers
• ✅ Scoreboard: monitor-based expected memory model
• ✅ Transaction logger: per-transfer logging + end-of-test summary

Timing & Stalls

• ✅ Configurable wait-state insertion (slave)
• ✅ Hold-stability during stalls
• ✅ Inter-transaction gap control (master)

Debug & Verification

• ✅ Interface-bound SVA assertions
  • Hold-stability while stalled
  • Known/X checks on control signals
  • AHB-Lite response legality
• ✅ Functional coverage
  • Read/write operations
  • Transfer sizes
  • Burst types and lengths
  • Wait state bins
  • Response types
  • Cross-coverage matrices

📋 Planned Features (Future Releases)

AHB Full Enhancements

• 📋 Multi-master arbitration support
• 📋 HMASTER behavior tracking
• 📋 SPLIT/RETRY response handling
• 📋 HSPLITx signal support

Protocol Enhancements

• 📋 BUSY insertion and legality checking
• 📋 Stricter wrap boundary alignment enforcement
• 📋 Endianness configuration (currently little-endian)
• 📋 Multiple slave regions with interconnect-like decode

Advanced Features

• 📋 Full UVM transaction recording (UVM TR) integration
• 📋 Performance monitoring and bottleneck analysis
• 📋 Advanced constrained random coverage
• 📋 Formal verification property exports

🔍 Debug Workflow

Recommended Bring-Up Sequence

1. Start with basic transfers:

   make questa TEST=ahb_smoke_test
   

   Verifies basic SINGLE read/write operations

2. Enable wait states:

   make questa TEST=ahb_wait_state_test
   

   Tests slave stall insertion and hold-stability

3. Enable burst stress:

   make questa TEST=ahb_back_to_back_test
   make questa TEST=ahb_random_stress_test
   

   Tests various burst types and random traffic

4. Enable error injection:

   make questa TEST=ahb_error_test
   

   Tests error response handling

Debug Options

# Verbose UVM messaging
+UVM_VERBOSITY=UVM_HIGH

# Enable transaction tracing
+VIP_TRACE

# Warn on uninitialized memory reads
+KVIPS_AHB_SB_WARN_UNINIT

# Waveform dumping
+KVIPS_WAVES

📚 Detailed Documentation

For comprehensive information, refer to the following source documents in ahb/docs/:

• User Guide - Detailed configuration and usage
• Integration Guide - Step-by-step integration
• Supported Features - Complete feature list
• Assertions - SVA checker documentation
• Testplan - Test coverage mapping
• Directory Structure - File organization

💡 Integration Example

Minimal Testbench Integration

// 1. Instantiate AHB interface
ahb_if ahb_if_inst (
    .HCLK(clk),
    .HRESETn(rst_n)
);

// 2. In your UVM environment
class my_env extends uvm_env;
    ahb_env ahb_env_inst;
    
    function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        
        // Create AHB configuration
        ahb_cfg cfg = ahb_cfg::type_id::create("cfg");
        cfg.mode = AHB_MODE_LITE;
        cfg.allow_wait_states = 1;
        cfg.max_wait = 5;
        cfg.trace_enable = 1;
        
        // Set virtual interface
        if (!uvm_config_db#(virtual ahb_if)::get(this, "", "vif", cfg.vif))
            `uvm_fatal("ENV", "Failed to get AHB interface")
        
        // Create environment
        uvm_config_db#(ahb_cfg)::set(this, "ahb_env_inst", "cfg", cfg);
        ahb_env_inst = ahb_env::type_id::create("ahb_env_inst", this);
    endfunction
endclass

// 3. Start sequences
class my_test extends uvm_test;
    task run_phase(uvm_phase phase);
        ahb_single_seq seq;
        phase.raise_objection(this);
        
        seq = ahb_single_seq::type_id::create("seq");
        seq.addr = 32'h1000;
        seq.data = 32'hDEADBEEF;
        seq.is_write = 1;
        seq.start(env.ahb_env_inst.master_agent.sequencer);
        
        phase.drop_objection(this);
    endtask
endclass

🎓 Example Tests

Located in kvips/ahb/examples/uvm_back2back/:

examples/
├── tb/
│   ├── top.sv                  # Top-level testbench
│   └── test_pkg.sv             # Test package
├── tests/
│   ├── ahb_base_test.sv
│   ├── ahb_smoke_test.sv
│   ├── ahb_wait_state_test.sv
│   ├── ahb_back_to_back_test.sv
│   └── ahb_random_stress_test.sv
└── sim/
    ├── Makefile
    ├── run_questa.sh
    ├── run_vcs.sh
    └── run_xcelium.sh

🔧 Validated Tool Versions

📞 Support & Resources