Verification IP Catalog

Explore our collection of professional-grade SystemVerilog UVM verification IPs, validated on leading EDA simulators.

🔌 Available VIPs

🔌

AXI4 Full

Stable v1.0 UVM 1.2

AMBA AXI4 Full Protocol

Complete master/slave verification IP for AMBA AXI4 (full) with extensive protocol checking and built-in scoreboard.

Key Features:
  • Master & Slave agents with configurable memory
  • All burst types: INCR, FIXED, WRAP
  • Exclusive access with reservation tracking
  • Pipelined outstanding transactions
  • Error injection (SLVERR, DECERR)
  • Comprehensive SVA protocol checkers
  • Performance statistics
Validated On:
Questa 2025.3_2 VCS 2025.06_1 Xcelium 25.03.007 Verilator 5.x
Documentation Quick Start
🔌

APB

Stable v1.0 UVM 1.2

Advanced Peripheral Bus

Master/slave VIP for AMBA APB3/APB4, ideal for low-bandwidth peripheral and register access verification.

Key Features:
  • Single-image APB3/APB4 support (runtime switch)
  • Configurable wait states
  • Error response injection
  • Protocol compliance checking
  • Monitor coverage + optional transaction recording
Validated On:
Questa 2025.3_2 VCS 2025.06_1 Xcelium 25.03.007 Verilator 5.x
Documentation Quick Start
🔗

AHB (AHB-Lite/Full)

Stable v1.0 UVM 1.2

Advanced High-performance Bus

Master/slave VIP for AMBA AHB-Lite and AHB Full, supporting burst transfers and pipelined operation.

Key Features:
  • Single-image AHB-Lite/Full support (runtime switch)
  • INCR4/8/16 and WRAP4/8/16 burst transfers
  • Variable HSIZE (byte to double-word)
  • Configurable wait states and stall handling
  • Error response injection (OKAY/ERROR)
  • Protocol compliance checking with SVA
  • Monitor-based scoreboard with coverage
Validated On:
Questa 2025.3_2 VCS 2025.06_1 Xcelium 25.03.007 Verilator 5.x
Documentation Quick Start

🗺️ VIP Roadmap

### Phase 1: Bus Protocols (In Progress)
Protocol Status Target Priority
AXI4 Full ✅ Complete v1.0 High
APB ✅ Stable v1.0 High
AHB ✅ Stable v1.0 Medium
AXI-Lite 📋 Planned Q2 2026 Medium
AXI-Stream 📋 Planned Q3 2026 Medium
### Phase 2: High-Speed Interfaces
Protocol Status Target Priority
PCIe 📋 Planned Q4 2026 High
USB 2.0 📋 Planned Q4 2026 Medium
USB 3.0 📋 Planned 2027 Low
Ethernet MAC 📋 Planned 2027 Medium
### Phase 3: Peripheral Interfaces
Protocol Status Target Priority
I2C 📋 Planned Q3 2026 Medium
SPI 📋 Planned Q3 2026 Medium
UART 📋 Planned Q3 2026 Low
GPIO 📋 Planned Q4 2026 Low

🎯 VIP Selection Guide

Choose the Right VIP

🚀 High Performance

Recommended VIPs:

  • AXI4 Full (pipelined mode)
  • AXI-Stream (coming soon)
  • PCIe (coming soon)

For high-bandwidth data transfer and DMA operations

📝 Register Access

Recommended VIPs:

  • APB (stable)
  • AXI-Lite (coming soon)
  • AHB (stable)

For configuration registers and low-bandwidth control

🔌 Peripherals

Recommended VIPs:

  • I2C (coming soon)
  • SPI (coming soon)
  • UART (coming soon)

For sensor interfaces and debug communications

📊 Feature Comparison

Feature AXI4 APB AHB PCIe
Master Agent ✅ ✅ ✅ 📋
Slave Agent ✅ ✅ ✅ 📋
Monitor ✅ ✅ ✅ 📋
Protocol Assertions ✅ ✅ ✅ 📋
Scoreboard ✅ ✅ ✅ 📋
Coverage ✅ ✅ ✅ 📋
Error Injection ✅ ✅ ✅ 📋
Performance Stats ✅ ✅ ✅ 📋

✅ Available     📋 Planned

🤝 Contributing

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