Frequently Asked Questions

KVIPS (K's Verification IP Suite) is a vendor-neutral, open-source library of SystemVerilog UVM verification components for protocol verification. It provides production-ready VIPs that work across multiple simulators.

Yes! KVIPS is released under the MIT License, which allows free use in both commercial and non-commercial projects. See the LICENSE file for full details.

KVIPS is validated on:

• Siemens Questa 2025.3_2
• Synopsys VCS 2025.06_1
• Cadence Xcelium 25.03.007

Absolutely! We welcome contributions. Please see our Contributing Guide for details on how to get started.

Yes, KVIPS assumes basic familiarity with UVM methodology. If you're new to UVM, we recommend:

• UVM 1.2 User Guide
• Online UVM tutorials
• Our Getting Started Guide

See our Getting Started Guide and Integration Guide for step-by-step instructions. The basic steps are:

1. Add KVIPS to your compilation
2. Instantiate the interface in your top module
3. Configure and create agents in your environment
4. Start sequences on the sequencers

Yes! KVIPS VIPs are designed to work together. You can instantiate multiple agents (same or different protocols) in your environment. See the multi-agent examples in the documentation.

Yes, all transaction classes use SystemVerilog constraints for randomization. You can:

• Use built-in constraints
• Add custom constraints via `uvm_do_with`
• Extend transaction classes with additional constraints
• Create custom sequences with specific randomization profiles

The AXI4 VIP supports:

• All burst types (INCR, FIXED, WRAP)
• Burst lengths up to 256 (INCR) or 16 (FIXED/WRAP)
• All data widths (8, 16, 32, 64, 128, 256, 512, 1024 bits)
• Exclusive accesses
• Multiple outstanding transactions
• Error responses (SLVERR, DECERR)
• Protocol assertions (SVA)
• Built-in scoreboard

Configure the master agent: ```systemverilog cfg.master_pipelined = 1; cfg.max_outstanding_writes = 16; cfg.max_outstanding_reads = 16; ``` Or use runtime plusarg: `+VIP_PIPE +VIP_MAX_OUTS=16`

Configure the slave agent: ```systemverilog cfg.slave_err_enable = 1; cfg.slave_err_start = 32'hF000; cfg.slave_err_end = 32'hFFFF; cfg.slave_err_resp = AXI4_RESP_SLVERR; cfg.slave_err_on_write = 1; cfg.slave_err_on_read = 1; ``` Now accesses to 0xF000-0xFFFF will return SLVERR.

Yes, use these plusargs:

• `+KVIPS_AXI4_ASSERT_OFF` - Disable all assertions
• `+KVIPS_AXI4_ASSERT_BURST_OFF` - Disable burst legality checks
• `+KVIPS_AXI4_ASSERT_EXCL_OFF` - Disable exclusive access checks
• `+KVIPS_AXI4_ASSERT_KNOWN` - Enable X/Z checks

Use any of these methods:

• Plusarg: `+VIP_TRACE`
• Config: `cfg.trace_enable = 1;`
• UVM verbosity: `+UVM_VERBOSITY=UVM_HIGH`
• Component-specific: `+uvm_set_verbosity=*driver*,UVM_DEBUG`

Use the plusarg `+KVIPS_WAVES` to enable wave dumping from the demo top:

• Default: VCD (`kvips_axi4_b2b.vcd`)
• Optional: FSDB when compiled with `FSDB` and the required Verdi/Novas PLI (see `axi4/examples/uvm_back2back/sim/run_questa_fsdb.sh`)

Common causes:

1. Missing handshakes: Ensure VALID/READY signals are driven
2. Clock/reset: Verify clock is toggling and reset is released
3. Configuration: Check agent is configured as active
4. Deadlock: Enable trace to see what's waiting
5. Timeout: Add timeout logic in your test

Steps to debug:

1. Read the error message carefully - it often points to the issue
2. Enable VIP trace: `+VIP_TRACE`
3. Check the line number and file in the error
4. Look for recent transaction activity before the error
5. Check assertions - they may have caught a protocol violation
6. Use waveforms to see signal-level activity

Performance tips:

• Disable assertions: `+KVIPS_AXI4_ASSERT_OFF`
• Reduce verbosity: `+UVM_VERBOSITY=UVM_LOW`
• Disable scoreboard if not needed: `+KVIPS_AXI4_SB_OFF`
• Use pipelined mode for throughput
• Minimize inter-transaction gaps
• Don't dump waveforms unless debugging
• Use sparse memory models

Memory usage depends on:

• Number of agents instantiated
• Memory model size (if using slave memory)
• Outstanding transaction limits
• Scoreboard history depth

Possibly, but not officially validated. We test on the versions listed above. Older versions may work if they support:

• SystemVerilog IEEE 1800-2012 or later
• UVM 1.1d or 1.2
• Parameterized classes
• SystemVerilog Assertions (SVA)

Not yet, but it's on the roadmap! We plan to add cocotb entry points for Python-based verification. Follow the repository for updates.

The SVA assertions can be used with formal tools for property verification. Full FPV testbenches are planned for future releases.

Yes! The MIT License allows commercial use. You can:

• Use KVIPS in commercial verification projects
• Modify and extend the code
• Distribute your modifications (optional)

Multiple support channels:

• Documentation: Check our comprehensive docs
• GitHub Issues: Report bugs or request features
• Discussions: Ask questions
• Email: For private inquiries

We currently offer community support through GitHub. For commercial support inquiries (training, custom development, consulting), please contact us directly.